Network processors requiring high memory bandwidth may use multi-port memory bit-cells, which are quite large and expensive to implement. For example, register file memories based on multi-port memory bit-cells may use 4-port memory bit-cells, each using four sets of pass gates, or 4-read port memory bit-cells using four sets of series transistors (e.g., NFET) for the read ports and pass gates for the write ports. These bit-cells, however, are substantially area expensive and can most commonly be used in small capacity register file application. The existing bit-cells and associated memory architectures are not suitable for use in large capacity memories as required by network processors.